The present invention relates to a semiconductor design technology, and more particularly, to a technology for controlling a program current.
Among various memory devices, a dynamic random access memory (DRAM), used as a computer main memory device, is capable of random access and high integration at a low cost. However, the DRAM has a drawback of being a volatile memory. While a static random access memory (SRAM), used as a cache memory, is capable of random access and is faster than the DRAM in the operating speed, the SRAM has a similar drawback. The SRAM is disadvantageous in terms of cost because it has a memory cell size larger than that of the DRAM. A NAND flash memory, which is a nonvolatile memory, is capable of high integration at a low cost and is advantageous in terms of power consumption. However, the NAND flash memory has a low operating speed because it is incapable of random access.
A phase-change random access memory (PCRAM) device is an example of various memory devices that have developed to overcome the drawbacks of such conventional memory devices. The PCRAM device is capable of random access and high integration at a low cost as a nonvolatile memory. The PCRAM device stores data using a phase changeable material. That is, the PCRAM device is a nonvolatile memory device that uses a phase change of a phase changeable material depending on the temperature conditions, i.e., a resistance change proportional to the phase change.
The phase changeable material has an amorphous state or a crystalline state depending on the temperature conditions. A typical example of the phase changeable material is a chalcogenide alloy, one of which, generally used, is Ge2Sb2Te5 (GST) using germanium (Ge), antimony (Sb), and tellurium (Te). The phase changeable material is generally called GST.
The PCRAM device generates a reversible phase change between the crystalline state and the amorphous state of the phase changeable material GST by using Joule heat generated by applying a specific current or voltage to the phase changeable material GST. The crystalline state of the phase changeable material GST is called a set state in terms of circuit. In the set state, the phase changeable material GST has electrical characteristics like a metal with a low resistance. The amorphous state of the phase changeable material GST is called a reset state in terms of circuit. In the reset state, the phase changeable material GST has a resistance higher than the set state. That is, the PCRAM device stores data on the basis of a resistance change between the crystalline state and the amorphous state, and reads the stored data by detecting a current change through the phase changeable material GST or a voltage change depending on a current change. In general, the set state is defined as having a logic level of ‘0’ and the reset state is defined as having a logic level of ‘1’. The phase changeable material GST maintains its state even when the power supply is interrupted.
Meanwhile, programming currents are used to make a change between the crystalline state and the amorphous state of the phase changeable material GST. A programming current, that is used to change the phase changeable material GST of a memory cell into the set state, is defined as a set current. A programming current, that is used to change the phase changeable material GST of a memory cell into the reset state, is defined as a reset current.
After the reset current is supplied to heat the phase changeable material GST for a given time at temperatures higher than a melting temperature, the phase changeable material GST cools rapidly and changes into the amorphous state. Also, if the set current is supplied to heat the phase changeable material GST for a given time at temperatures higher than a crystallization temperature and lower than the melting temperature, and then, the phase changeable material GST cools gradually and changes into the crystalline state. Meanwhile, because resistance values can be differentiated according to the crystalline volume or the amorphous volume of the phase changeable material GST, this can be used to construct a multi-level memory cell. In general, the reset current is higher than the set current and is flowed for a short time in comparison with the set current; and the set current is lower than the reset current and is flowed for a long time in comparison with the reset current. That is, the state of the phase changeable material GST is changed by a Joule heat of specific conditions generated by supply of the programming currents.
FIG. 1 is a diagram illustrating a structure of a phase-change memory cell.
Referring to FIG. 1, a phase-change memory cell includes: a phase changeable element GST connected between a bit line BL and a first node NO; and a cell transistor MN1 connected between the first node NO and a ground voltage terminal VSS and controlled by a word line WL.
The above phase-change memory cell operates as follows.
First, an operation for programming data in the phase changeable element GST is as follows.
When the word line WL is activated to a high level to turn on the cell transistor MN1, a current path is formed between the ground voltage terminal VSS and the phase changeable element GST connected to the bit line BL. Thus, when a programming current corresponding to data is supplied to the phase changeable element GST through the bit line BL, the phase changeable element GST changes into a crystalline state or an amorphous state. In general, when programming data having a logic level of ‘1’, a reset current is supplied to change the phase changeable element GST into a reset state; and when programming data having a logic level of ‘0’, a set current is supplied to change the phase changeable element GST into a set state. The reset state, i.e., the amorphous state has a greater resistance value than the set state, i.e., the crystalline state.
Also, an operation for detecting data programmed in the phase changeable element GST is as follows.
When the word line WL is activated to a high level to turn on the cell transistor MN1, a current path is formed between the ground voltage terminal VSS and the phase changeable element GST connected to the bit line BL. Thus, when a given voltage or a given current is applied to the phase changeable element GST through the bit line BL, because the flowing current amount or the voltage drop level of the phase changeable element GST differs depending on the resistance value of the phase changeable element GST, this is used to determine data stored in the phase changeable element GST, that is, to determine the state of the phase changeable element GST.
FIG. 2 is a diagram illustrating another structure of a phase-change memory cell.
Referring to FIG. 2, a phase-change memory cell includes: a cell diode D1 having a cathode connected to a word line WL and an anode connected to a first node NO; and a phase changeable element GST connected between a bit line BL and the first node NO.
The above phase-change memory cell operates as follows.
First, an operation for programming data in the phase changeable element GST is as follows.
When the word line WL is activated to a low level, i.e., a ground voltage level and a given voltage starts to be applied through the bit line BL, the cell diode D1 becomes a forward bias state. Therefore, the cell diode D1 is turned on when the voltage difference between the cathode and the anode of the cell diode D1 becomes greater than a threshold voltage. At this point, a current path is formed between the word line WL and the phase changeable element GST connected to the bit line BL. Thus, when a programming current corresponding to data is supplied to the phase changeable element GST through the bit line BL, the phase changeable element GST changes into a crystalline state or an amorphous state. In general, when programming data having a logic level of ‘1’, a reset current is supplied to change the phase changeable element GST into a reset state; and when programming data having a logic level of ‘0’, a set current is supplied to change the phase changeable element GST into a set state. The reset state, i.e., the amorphous state has a greater resistance value than the set state, i.e., the crystalline state.
Also, an operation for detecting data programmed in the phase changeable element GST is as follows.
When the word line WL is activated to a low level, i.e., a ground voltage level and a given voltage starts to be applied through the bit line BL, the cell diode D1 becomes a forward bias state. Therefore, the cell diode D1 is turned on when the voltage difference between the cathode and the anode of the cell diode D1 becomes greater than the threshold voltage. At this point, a current path is formed between the word line WL and the phase changeable element GST connected to the bit line BL. Thus, when a given voltage or a given current is applied to the phase changeable element GST through the bit line BL, because the flowing current amount or the voltage drop level of the phase changeable element GST differs depending on the resistance value of the phase changeable element GST, this is used to determine data stored in the phase changeable element GST, that is, to determine the state of the phase changeable element GST.
The structure of the phase-change memory cell of FIG. 2, which uses the cell diode D1 instead of the cell transistor, has good programming current supply characteristics because of the diode characteristics and is advantageous for high integration because of its small occupying area. Thus, a cell diode, rather than a cell transistor, is recently used to construct a phase-change memory cell.
Meanwhile, the resistance values can be differentiated according to the crystalline volume or the amorphous volume of the phase changeable material GST as described above, and these characteristics can be used to construct a multi level cell (MLC)-type phase-change memory cell. A phase-change memory device including the MLC-type phase-change memory cell is very high in competitiveness because it can be implemented in a higher integration level than a phase-change memory device including a single level cell (SLC)-type phase-change memory cell. What is therefore required is a circuit for controlling the MLC-type phase-change memory cell.